Datasheet

Section 14 Watchdog Timer (WDT)
R01UH0310EJ0500 Rev. 5.00 Page 861 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
14.6 Usage Notes
14.6.1 Notes on Register Access
The watchdog timer's TCNT, TCSR, and RSTCSR registers differ from other registers in being
more difficult to write to. The procedures for writing to and reading these registers are given
below.
(1) Writing to TCNT, TCSR, and RSTCSR
TCNT and TCSR must be written to by a word transfer instruction. They cannot be written to by a
byte transfer instruction.
TCNT and TCSR both have the same write address. Therefore, satisfy the relative condition
shown in figure 14.4 to write to TCNT or TCSR. The transfer instruction writes the lower byte
data to TCNT or TCSR according to the satisfied condition.
To write to RSTCSR, execute a word transfer instruction for address H'FFBE. A byte transfer
instruction cannot perform writing to RSTCSR.
The method of writing 0 to the WOVF bit differs from that of writing to the RSTE bit. To write 0
to the WOVF bit, satisfy the lower condition shown in figure 14.4.
If satisfied, the transfer instruction clears the WOVF bit to 0, but has no effect on the RSTE bit.
To write to the RSTE bit, satisfy the above condition shown in figure 14.4. If satisfied, the transfer
instruction writes the value in bit 6 of the lower byte into the RSTE bit, but has no effect on the
WOVF bit.