Datasheet

Section 10 I/O Ports
Page 568 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
• P20/PO0-A/TIOCA3-A/TMRI0-A
The pin function is switched as shown below according to the combination of the TPU channel
3 settings (by bits MD3 to MD0 in TMDR_3, bits IOA3 to IOA0 in TIORH_3, and bits
CCLR2 to CCLR0 in TCR_3), bit NDER0 in NDERL of the PPG, bits PPGS, TPUS, and
TMRS in PFCR3, and bit P20DDR.
TPU channel 3
settings
(1) in table
below
(2) in table below
P20DDR ⎯ 0 1
NDER0 ⎯ ⎯ 0 1
P20 input P20 output PO0-A output*
4
TIOCA3-A
output*
5
TIOCA3-A input*
1
*
5
Pin function
TMRI0-A input*
2
*
6
TPU channel 3
settings
(2) (1) (2) (1) (1) (2)
MD3 to MD0 B'0000 B'001x B'0010 B'0011
IOA3 to IOA0 B'0000,
B'0100,
B'1xxx
B'0001 to
B'0011,
B'0101 to
B'0111
B'xx00 Other than
B'xx00
Other than B'xx00
CCLR2 to
CCLR0
⎯ ⎯ ⎯ ⎯ Other than
B'001
B'001
Output function ⎯ Output
compare
output
⎯ PWM*
3
mode
1 output
PWM mode
2 output
⎯
[Legend]
x: Don't care
Notes: 1. TIOCA3-A input when MD3 to MD0 = B'0000 and IOA3 to IOA0 = B'10xx.
2. When used as the counter reset input pin for the TMR, the external reset should be
selected using the CCLR1 and CCLR0 bits in TCR_0 and TMRIS bit in TCCR_0 after
the TMRS bit in PFCR3 is set to 0.
3. TIOCB3 output disabled.
4. When using as PO0-A output, set PPGS in PFCR3 to 0 before other register setting.
5. When using as TIOCA3-A input/output, set TPUS in PFCR3 to 0 before other register
setting.
6. When using as TMRI0-A input, set TMRS in PFCR3 to 0 before other register setting.