Datasheet

Section 10 I/O Ports
R01UH0310EJ0500 Rev. 5.00 Page 539 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
SSU settings (1) (2) (1) (3) (1) (2) (1) (3)
SSUMS 0 1
MSS 0 1 0 1
SCKS 0 1 0 1 0 1 0 1
Pin state ⎯ SSCK
input
⎯ SSCK
output
⎯ SSCK
input
⎯ SSCK
output
[Legend]
⎯: Not used as the SSU pin (can be used as an I/O port).
Note: See tables 19.4 to 19.6.
• P15/DACK1/PO13/TIOCB1/TCLKC/SSI0-A
The pin function is switched as shown below according to the combination of bit SAE1 in
DMABCRH of the DMAC, TPU channel 1 settings (by bits MD3 to MD0 in TMDR_1, bits
IOB3 to IOB0 in TIOR_1, and bits CCLR1 and CCLR0 in TCR_1), bits TPSC2 to TPSC0 in
TCR_0, TCR_2, TCR_4, and TCR_5, bit NDER13 in NDERH of the PPG, bits MSS and
BIDE in SSCRH, bit SSUMS in SSCRL, and bits TE and RE in SSER of the SSU, bits SSI0S1
and SSI0S0 in PFCR5, and bit P15DDR.
SSU settings (1) in table below (2) in table
below
(3) in table
below
SAE1 0 1 ⎯
TPU channel 1
settings
(1) in table
below
(2) in table below ⎯ ⎯
P15DDR ⎯ 0 1 1 ⎯ 0*
5
⎯
NDER13 ⎯ ⎯ 0 1 ⎯ ⎯
P15
input
P15
output
PO13
output
DACK1
output
TIOCB1
output
TIOCB1 input*
1
Pin function
TCLKC input*
2
SSI0-A
input*
3
*
6
SSI0-A
output*
4
*
6
Notes: 1. TIOCB1 input when MD3 to MD0 = B'0000 or B'01xx and IOB3 to IOB0 = B'10xx.
2. TCLKC input when the setting for either TCR_0 or TCR_2 is TPSC2 to TPSC0 = B'111,
or when the setting for either TCR_4 or TCR_5 is TPSC2 to TPSC0 = B'101. TCLKC
input when phase counting mode is set for channels 2 and 4.
3. When using as SSI0-A input, set SSI0S1 and SSI0S0 in PFCR5 to B'00 before other
register setting.
4. When using as SSI0-A output, set SSI0S1 and SSI0S0 in PFCR5 to B'00 before other
register setting.
5. P15DDR = 0 when the SSU pin is used as input.
6. Do not set up for SSU unless SSI0S1 and SSI0S0 = B'00 in PFCR5.
Use as I/O port, TPU, or DMAC pin.