Datasheet

Section 10 I/O Ports
R01UH0310EJ0500 Rev. 5.00 Page 533 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
TPU channel 0
settings
(2) (1) (2) (1) (1) (2)
MD3 to MD0 B'0000 B'001x B'0010 B'0011
IOC3 to IOC0 B'0000,
B'0100,
B'1xxx
B'0001 to
B'0011,
B'0101 to
B'0111
B'xx00 Other than
B'xx00
Other than B'xx00
CCLR2 to
CCLR0
⎯ ⎯ ⎯ ⎯ Other than
B'101
B'101
Output function ⎯ Output
compare
output
⎯ PWM*
3
mode 1
output
PWM mode
2 output
⎯
[Legend]
x: Don't care
Notes: 1. TIOCC0 input when MD3 to MD0 = B'0000 and IOC3 to IOC0 = B'10xx.
2. TCLKA input when the setting for any of TCR_0 to TCR_5 is TPSC2 to TPSC0 = B'100.
TCLKA input when phase counting mode is set for channels 1 and 5.
3. TIOCD0 output disabled. Output disabled and settings (2) effective when BFA = 1 or
BFB = 1 in TMDR_0.
• P11/PO9/TIOCB0
The pin function is switched as shown below according to the combination of the TPU channel
0 settings (by bits MD3 to MD0 in TMDR_0, bits IOB3 to IOB0 in TIORH_0, and bits
CCLR2 to CCLR0 in TCR_0), bit NDER9 in NDERH of the PPG, and bit P11DDR.
TPU channel 0
settings
(1) in table below (2) in table below
P11DDR ⎯ 0 1
NDER9 ⎯ ⎯ 0 1
P11 input P11 output PO9 output Pin function TIOCB0 output
TIOCB0 input*
Note: * TIOCB0 input when MD3 to MD0 = B'0000 and IOB3 to IOB0 = B'10xx.