Datasheet

Section 7 DMA Controller (DMAC)
R01UH0310EJ0500 Rev. 5.00 Page 327 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
(2) Full Address Mode
• DMACR_0A and DMACR_1A
Bit Bit Name Initial Value R/W Description
15 DTSZ 0 R/W Data Transfer Size
Selects the size of data to be transferred at one
time.
0: Byte-size transfer
1: Word-size transfer
14
13
SAID
SAIDE
0
0
R/W
R/W
Source Address Increment/Decrement
Source Address Increment/Decrement Enable
These bits specify whether source address
register MARA is to be incremented,
decremented, or left unchanged, when data
transfer is performed.
00: MARA is fixed
01: MARA is incremented after a data transfer
• When DTSZ = 0, MARA is incremented by 1
• When DTSZ = 1, MARA is incremented by 2
10: MARA is fixed
11: MARA is decremented after a data transfer
• When DTSZ = 0, MARA is decremented by 1
• When DTSZ = 1, MARA is decremented by 2
12
11
BLKDIR
BLKE
0
0
R/W
R/W
Block Direction
Block Enable
These bits specify whether normal mode or block
transfer mode is to be used for data transfer. If
block transfer mode is specified, the BLKDIR bit
specifies whether the source side or the
destination side is to be the block area.
x0: Transfer in normal mode
01: Transfer in block transfer mode (destination
side is block area)
11: Transfer in block transfer mode (source side is
block area)