Datasheet

Section 7 DMA Controller (DMAC)
R01UH0310EJ0500 Rev. 5.00 Page 323 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
7.3.4 DMA Control Registers (DMACRA and DMACRB)
DMACR controls the operation of each DMAC channel.
The DMA has four DMACR registers: DMACR_0A in channel 0 (channel 0A), DMACR_0B in
channel 0 (channel 0B), DMACR_1A in channel 1 (channel 1A), and DMACR_1B in channel 1
(channel 1B). In short address mode, channels A and B operate independently, and in full address
mode, channels A and B operate together. The bit functions in the DMACR registers differ
according to the transfer mode.
(1) Short Address Mode
• DMACR_0A, DMACR_0B, DMACR_1A, and DMARC_1B
Bit Bit Name Initial Value R/W Description
7 DTSZ 0 R/W Data Transfer Size
Selects the size of data to be transferred at one
time.
0: Byte-size transfer
1: Word-size transfer
6 DTID 0 R/W Data Transfer Increment/Decrement
Selects incrementing or decrementing of MAR
after every data transfer in sequential mode or
repeat mode. In idle mode, MAR is neither
incremented nor decremented.
0: MAR is incremented after a data transfer
(Initial value)
• When DTSZ = 0, MAR is incremented by 1
• When DTSZ = 1, MAR is incremented by 2
1: MAR is decremented after a data transfer
• When DTSZ = 0, MAR is decremented by 1
• When DTSZ = 1, MAR is decremented by 2