Datasheet

Section 1 Overview
R01UH0310EJ0500 Rev. 5.00 Page 3 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
Type
Module/
Function Description
CPU MCU
operating
mode
• Mode 1: Expanded mode with on-chip ROM disabled,
16-bit bus (MD2 and MD1 pins are low and MD0
pin is high)
• Mode 2: Expanded mode with on-chip ROM disabled,
8-bit bus (MD2 pin is low, MD1 pin is high, and
MD0 pin is low)
• Mode 3: Boot mode (MD2 pin is low and MD1 and MD0 pins
are high)
• Mode 4: Expanded mode with on-chip ROM enabled,
8-bit bus (MD2 pin is high and MD1 and MD0 pins
are low)
• Mode 7: Single-chip mode (MD2, MD1, and MD0 pins are
high)
• Power-down modes (a power-down mode is entered when the
SLEEP instruction is executed)
Interrupts
(sources)
Interrupt
controller
• External interrupt pins
H8S/2426 Group, H8S/2426R Group:
33 pins (NMI, IRQ15-A to IRQ0-A, IRQ15-B to IRQ0-B)
H8S/2424 Group:
17 pins (NMI, IRQ7-A to IRQ0-A, IRQ7-B to IRQ0-B)
• Internal interrupt sources
H8S/2426 Group, H8S/2426R Group: 96 sources
H8S/2424 Group: 94 sources
• Two interrupt control modes (specified by the interrupt control
register)
• Eight priority levels can be set (specified by the interrupt priority
registers)
• Independent vector addresses
DMA DMA
controller
(DMAC)
• DMA transfer is possible on four channels
• Three activation sources (auto-request, on-chip module interrupt,
and external request)
• Byte or word can be set as the transfer unit
• Short address mode or full address mode can be selected
• 16-Mbyte address space can be specified directly