Datasheet

Section 3 MCU Operating Modes
Rev. 3.00 Sep. 28, 2009 Page 54 of 710
REJ09B0384-0300
3.2.3 Serial Timer Control Register (STCR)
STCR enables or disables register access, IIC operating mode, and on-chip flash memory, and
selects the input clock of the timer counter.
Bit Bit Name Initial Value R/W Description
7
6
5
IICX2
IICX1
IICX0
0
0
0
R/W
R/W
R/W
IIC Transfer Rate Select 2, 1 and 0
These bits control the IIC operation. These bits
select a transfer rate in master mode together with
bits CKS2 to CKS0 in the I
2
C bus mode register
(ICMR). For details on the transfer rate, see table
15.3. The IICXn bit controls IIC_n. (n = 0 to 2)
4 ⎯ 0 R/W Reserved
The initial value should not be changed.
3 FLSHE 0 R/W Flash Memory Control Register Enable
Enables or disables CPU access for flash memory
registers (FCCS, FPCS, FECS, FKEY, FMATS,
FTDAR), control registers of power-down states
(SBYCR, LPWRCR, MSTPCRH, MSTPCRL), and a
control register of on-chip peripheral modules
(PCSR).
0: Area from H'FFFE88 to H'FFFE8F is reserved.
Control registers of power-down states and on-
chip peripheral modules are accessed in an area
from H'FFFF80 to H'FFFF87.
1: Control registers of flash memory are accessed in
an area from H'FFFE88 to H'FFFE8F.
Area from H'FFFF80 to H'FFFF87 is reserved.
2 ⎯ 1 R/W Reserved
The initial value should not be changed.
1
0
ICKS1
ICKS0
0
0
R/W
R/W
Internal Clock Source Select 1, 0
These bits select a clock to be input to the timer
counter (TCNT) and a count condition together with
bits CKS2 to CKS0 in the timer control register
(TCR). For details, see section 11.2.4, Timer Control
Register (TCR).