Datasheet

Section 2 CPU
Rev. 3.00 Sep. 28, 2009 Page 48 of 710
REJ09B0384-0300
End of bus request
Bus request
Program execution
state
Bus-released state
Sleep mode
Exception-handling state
Software standby mode
RES = high
Reset state
STBY = High, RES = Low
Hardware standby mode
*2
Power-down state
*1
Notes: 1.
2.
From any state except hardware standby mode, a transition to the reset state occurs whenever
RES
goes low. A transition can also be made to the reset state when the watchdog timer overflows.
From any state, a transition to hardware standby mode occurs when
STBY
goes low.
SLEEP
instruction
with
SSBY = 0
Interrupt
request
End of bus
request
Bus
request
Request for
exception
handling
End of
exception
handling
External interrupt
request
SLEEP
instruction
with
PSS = 0 and
SSBY = 1
Figure 2.13 State Transitions