Datasheet

Rev. 3.00 Sep. 28, 2009 Page 706 of 710
REJ09B0384-0300
Effective address extension ...................... 40
ERI1........................................................ 310
ERI2........................................................ 310
Error protection ...................................... 571
Exception handling................................... 57
Exception handling vector table ............... 58
Extended control register (EXR) .............. 23
External clock......................................... 627
F
Flash MAT configuration ....................... 513
FOVI....................................................... 204
Framing error.......................................... 278
G
General registers....................................... 22
H
Hardware protection ............................... 569
Hardware standby mode ......................... 645
I
I/O ports.................................................. 125
I
2
C bus formats....................................... 359
I
2
C bus interface (IIC) ............................ 327
Input pull-up MOS control register ........ 125
Input pull-up MOSs................................ 125
Instruction set ........................................... 29
Arithmetic operations instructions........ 32
Bit manipulation instructions................ 35
Block sata transfer instructions............. 39
Branch instructions............................... 37
Data transfer instructions...................... 31
Logic operations instructions................ 34
Shift instructions................................... 34
System control instructions...................38
Interface ..................................................251
Internal block diagram ................................3
Interrupt control modes.............................78
Interrupt controller....................................65
Interrupt exception handling.....................62
Interrupt exception handling sequence......85
Interrupt exception handling vector
table...........................................................76
Interrupt mask bit......................................24
interrupt mask level...................................23
Interval timer mode.................................243
IRQ15 to IRQ0 interrupts .........................74
L
LPC interface (LPC) ...............................405
LSI internal states in each mode .............640
M
Master receive operation.........................365
Master transmit operation .......................361
Medium-speed mode...............................641
Mode comparison....................................512
Mode transition diagram.........................639
Module stop mode...................................646
Multiply-accumulate register (MAC) .......25
Multiprocessor communication
function ...................................................282
N
NMI interrupt............................................74
Normal transfer mode .....................113, 121
Number of DTC execution states............118