Datasheet

Rev. 3.00 Sep. 28, 2009 Page 703 of 710
REJ09B0384-0300
Item Page Revision (See Manual for Details)
15.4.4 Master Receive
Operation
Figure 15.12 Stop
Condition Issuance
Timing Example in
Master Receive Mode
(MLS = WAIT = 0, HNDS
= 1)
368 Figure amended
SDA
(master output)
SDA
(slave output)
21
4
3
65
8
7
9978
A
A
Bit 7Bit 1
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
IRIC
ICDRF
ICDRR
SCL
(master output)
Data 3
Data 2
Data 1 Data 2
Data 3
[9] IRIC clear
User processing
IRTR
[8] [3]
Bit 0
[11] BBSY cleared to 0 and
SCP cleared to 0
(Stop condition instruction issuance)
[4] IRIC clear [7] ICDR read
(Data 2)
[10] ICDR read
(Data 3)
[6] ACKB set to 1
Bit 0
Stop condition generation
SCL is fixed low until ICDR is read SCL is fixed low until ICDR is read
16.3.2 Host Interface
Control Registers 2 and
3 (HICR2 and HICR3)
• HICR3
417 Table amended
Bit
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
—
—
—
—
—
—
—
—
LFRAME
—
SERIRQ
LRESET
—
—
—
—
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Bit Name Initial Value Slave DescriptionHost
R/W
0: LFRAME Pin state is low level
1: LFRAME Pin state is high level
Reserved
0: SERIRQ Pin state is low level
1: SERIRQ Pin state is high level
0: LRESET Pin state is low level
1: LRESET Pin state is high level
Reserved
Reserved
Reserved
Reserved