Datasheet

Appendix
Rev. 3.00 Sep. 28, 2009 Page 697 of 710
REJ09B0384-0300
Appendix
A. I/O Port States in Each Processing State
Table A.1 I/O Port States in Each Processing State
Port Name
Pin Name Reset
Hardware
Standby Mode
Software
Standby Mode Sleep Mode
Program
Execution State
Port 1
T T kept kept I/O port
Port 2
T T kept kept I/O port
Port 3
T T kept kept I/O port
Port 4
T T kept kept I/O port
Port 57
T T kept kept I/O port
Port 56
φ, EXCL
T T [DDR = 1] : H
[DDR = 0] : T
[DDR = 1] :
Clock output
[DDR = 0] : T
Clock output/
EXCL input/
Input port
Port 53, 52
T T kept kept I/O port
Port 6
T T kept kept I/O port
Port 7
T T T T Input port
Port 8
T T kept kept I/O port
Port A
T T kept kept I/O port
Port C
T T kept kept I/O port
Port E
T T kept kept I/O port
[Legend]
H: High level
L: Low level
T: High impedance
kept: Input port pins are in the high-impedance state (when DDR = 0 and PCR = 1, the input pull-
up MOS remains on).
Output port pins retain their states.
Functions of some pins will be changed to the I/O port function, which is determined by
DDR and DR, because the on-chip peripheral module associated with that pin function is
initialized.
DDR: Data direction register