Datasheet

Section 24 Electrical Characteristics
Rev. 3.00 Sep. 28, 2009 Page 691 of 710
REJ09B0384-0300
Table 24.11 JTAG Timing
Condition: VCC = 3.0 V to 3.6 V, VSS = 0 V, φ = 20 MHz to 25 MHz
Item Symbol Min. Max. Unit Test Conditions
ETCK clock cycle time t
TCKcyc
40* 50* ns Figure 24.20
ETCK clock high pulse width t
TCKH
15 ⎯
ETCK clock low pulse width t
TCKL
15 ⎯
ETCK clock rise time t
TCKr
⎯ 5
ETCK clock fall time t
TCKf
⎯ 5
ETRST pulse width t
TRSTW
20 ⎯ t
cyc
Figure 24.21
Reset hold transition pulse width t
RSTHW
3 ⎯
ETMS setup time t
TMSS
20 ⎯ ns Figure 24.22
ETMS hold time t
TMSH
20 ⎯
ETDI setup time t
TDIS
20 ⎯
ETDI hold time t
TDIH
20 ⎯
ETDO data delay time t
TDOD
⎯ 20
Note: * When t
cyc
≤ t
TCKcyc
ETCK
t
TCKcyc
t
TCKH
t
TCKf
t
TCKL
t
TCKr
Figure 24.20 JTAG ETCK Timing