Datasheet

Section 24 Electrical Characteristics
Rev. 3.00 Sep. 28, 2009 Page 689 of 710
REJ09B0384-0300
t
BUF
t
STAH
t
STAS
t
SP
t
STOS
t
SCLH
t
SCLL
t
Sf
t
Sr
t
SCL
t
SDAH
t
SDAS
P* S* Sr* P*
V
IH
V
IL
SDA0
to
SDA3
SCL0
to
SCL3
Note: * S, P, and Sr indicate the following conditions:
S: Start condition
P: Stop condition
Sr: Retransmission start condition
Figure 24.18 I
2
C Bus Interface Input/Output Timing
Table 24.10 LPC Module Timing
Conditions: VCC = 3.0 V to 3.6V, VSS = 0 V, φ = 20 MHz to 25 MHz
Item Symbol Min. Typ. Max. Unit Test Conditions
Input clock cycle t
Lcyc
30 ⎯ ⎯ ns Figure 24.19
Input clock pulse width (H) t
LCKH
11 ⎯ ⎯
Input clock pulse width (L) t
LCKL
11 ⎯ ⎯
Transmit signal delay time t
TXD
2 ⎯ 11
Transmit signal floating
delay time
t
OFF
⎯ ⎯ 28
Receive signal setup time t
RXS
7 ⎯ ⎯
Receive signal hold time t
RXH
0 ⎯ ⎯