Datasheet

Section 24 Electrical Characteristics
Rev. 3.00 Sep. 28, 2009 Page 685 of 710
REJ09B0384-0300
24.3.3 Timing of On-Chip Peripheral Modules
Tables 24.8 to 24.11 show the on-chip peripheral module timing. The on-chip peripheral modules
that can be operated by the subclock (φSUB = 32.768 kHz) are I/O ports, external interrupts (NMI
and IRQ0 to IRQ15), watchdog timer, and 8-bit timer (channels 0 and 1) only.
Table 24.8 Timing of On-Chip Peripheral Modules
Condition: VCC = 3.0 V to 3.6 V, VSS = 0 V, φ = 20 MHz to 25 MHz
Item Symbol Min. Max. Unit Test Conditions
I/O ports Output data delay time t
PWD
⎯ 30 ns
Input data setup time t
PRS
20 ⎯
Input data hold time t
PRH
20 ⎯
Figure 24.12
PWMX Timer output delay time t
PWOD
⎯ 30 ns Figure 24.13
SCI Input clock cycle Asynchronous t
Scyc
4 ⎯ t
cyc
Synchronous 6 ⎯
Input clock pulse width t
SCKW
0.4 0.6 t
Scyc
Input clock rise time t
SCKr
⎯ 1.5 t
cyc
Input clock fall time t
SCKf
⎯ 1.5
Figure 24.14
Transmit data delay time
(synchronous)
t
TXD
⎯ 30 ns
Receive data setup time
(synchronous)
t
RXS
20 ⎯
Receive data hold time
(synchronous)
t
RXH
20 ⎯
Figure 24.15
A/D
converter
Trigger input setup time t
TRGS
20 ⎯ ns Figure 24.16
WDT RESO output delay time t
RESD
⎯ 50 ns Figure 24.17
RESO output pulse width t
RESOW
132 ⎯ t
cyc