Datasheet

Section 24 Electrical Characteristics
Rev. 3.00 Sep. 28, 2009 Page 682 of 710
REJ09B0384-0300
t
EXH
t
EXL
t
EXr
t
EXf
V
CC
× 0.5
EXTAL
Figure 24.7 External Clock Input Timing
t DEXT *
RES
(Internal and external)
EXTAL
STBY
VCC
2.7 V
V
IH
φ
Note: The external clock output stabilization delay time (t
DEXT ) includes a RES pulse width (t RESW ).
Figure 24.8 Timing of External Clock Output Stabilization Delay Time