Datasheet

Section 24 Electrical Characteristics
Rev. 3.00 Sep. 28, 2009 Page 680 of 710
REJ09B0384-0300
Table 24.5 External Clock Input Conditions
Condition: VCC = 3.0 V to 3.6 V, VSS = 0 V, φ = 20 MHz to 25 MHz
Item Symbol Min. Max. Unit
Test
Conditions
External clock input low level
pulse width
t
EXL
80 ⎯ ns
External clock input high level
pulse width
t
EXH
80 ⎯ ns
External clock input rising time t
EXr
⎯ 5 ns
External clock input falling time t
EXf
⎯ 5 ns
Figure 24.7
Clock low level pulse width t
CL
0.4 0.6 t
cyc
Clock high level pulse width t
CH
0.4 0.6 t
cyc
Figure 24.4
External clock output
stabilization delay time
t
DEXT
* 500 ⎯ μs Figure 24.8
Note: * t
DEXT
includes a RES pulse width (t
RESW
).
Table 24.6 Subclock Input Conditions
Condition: VCC = 3.0 V to 3.6 V, VSS = 0 V, φ = 20 MHz to 25 MHz
Item Symbol Min. Typ. Max. Unit
Test
Conditions
Subclock input low level pulse
width
t
EXCLL
⎯ 15.26 ⎯ μs
Subclock input high level pulse
width
t
EXCLH
⎯ 15.26 ⎯ μs
Subclock input rising time t
EXCLr
⎯ ⎯ 10 ns
Subclock input falling time t
EXCLf
⎯ ⎯ 10 ns
Figure 24.9
Clock low level pulse width t
CL
0.4 ⎯ 0.6 t
cyc
Figure 24.4
Clock high level pulse width t
CH
0.4 ⎯ 0.6 t
cyc