Datasheet

Section 22 Power-Down Modes
Rev. 3.00 Sep. 28, 2009 Page 642 of 710
REJ09B0384-0300
φ
,
Bus master clock
peripheral module clock
Internal address bus
Internal write signal
Medium-speed mode
SBYCRSBYCR
Figure 22.2 Medium-Speed Mode Timing
22.4 Sleep Mode
The CPU makes a transition to sleep mode if the SLEEP instruction is executed when the SSBY
bit in SBYCR is cleared to 0. In sleep mode, CPU operation stops but the peripheral modules do
not stop. The contents of the CPU’s internal registers are retained.
Sleep mode is exited by any interrupt, the RES pin, or the STBY pin.
When an interrupt occurs, sleep mode is exited and interrupt exception handling starts. Sleep
mode is not exited if the interrupt is disabled, or interrupts other than NMI are masked by the
CPU.
Setting the RES pin level low cancels sleep mode and selects the reset state. After the oscillation
settling time has passed, driving the RES pin high causes the CPU to start reset exception
handling.
When the STBY pin level is driven low, a transition is made to hardware standby mode.