Datasheet

Section 22 Power-Down Modes
Rev. 3.00 Sep. 28, 2009 Page 635 of 710
REJ09B0384-0300
22.1.2 Low-Power Control Register (LPWRCR)
LPWRCR controls power-down modes.
Bit Bit Name
Initial
Value
R/W Description
7, 6 ⎯ 0 R/W
Reserved
The initial value should not be changed.
5 NESEL 0 R/W Noise Elimination Sampling Frequency Select
Selects the frequency by which the subclock (φSUB) input
from the EXCL pin is sampled using the clock (φ)
generated by the system clock pulse generator.
0: Sampling using φ/32 clock
1: Sampling using φ/4 clock
4 EXCLE 0 R/W Subclock Input Enable
Enables/disables subclock input from the EXCL pin.
0: Disables subclock input from the EXCL pin
1: Enables subclock input from the EXCL pin
3 to 0 ⎯ All 0 R/W Reserved
The initial value should not be changed.