Datasheet

Section 22 Power-Down Modes
Rev. 3.00 Sep. 28, 2009 Page 633 of 710
REJ09B0384-0300
Bit Bit Name
Initial
Value
R/W Description
6
5
4
STS2
STS1
STS0
0
0
0
R/W
R/W
R/W
Standby Timer Select 2 to 0
Select the wait time for clock settling from clock oscillation
start when canceling software standby mode. Select a
wait time of 8 ms (oscillation settling time) or more,
depending on the operating frequency.
With an external clock, select a wait time of 500 μs
(external clock output settling delay time) or more,
depending on the operating frequency.
Table 22.1 shows the relationship between the STS2 to
STS0 values and wait time.
3 DTSPEED 0 R/W DTC Speed
Specifies the operating clock for the bus masters (DTC)
other than the CPU in medium-speed mode.
0: All bus masters operate based on the medium-speed
clock.
1: The DTC operates based on the system clock.
The operating clock is changed when a DTC transfer is
requested even if the CPU operates based on the
medium-speed clock.
2
1
0
SCK2
SCK1
SCK0
0
0
0
R/W
R/W
R/W
System Clock Select 2 to 0
Select a clock for the bus master in high-speed mode or
medium-speed mode.
000: High-speed mode (Initial value)
001: Medium-speed clock: φ/2
010: Medium-speed clock: φ/4
011: Medium-speed clock: φ/8
100: Medium-speed clock: φ/16
101: Medium-speed clock: φ/32
11x: Must not be set.
[Legend]
x: Don't care