Datasheet

Section 21 Clock Pulse Generator
Rev. 3.00 Sep. 28, 2009 Page 629 of 710
REJ09B0384-0300
21.7 Clock Select Circuit
The clock select circuit selects the system clock that is used in this LSI.
A clock generated by the oscillator, to which the EXTAL and XTAL pins are input, and multiplied
by the PLL circuit is selected as a system clock when returning from high-speed mode, medium-
speed mode, sleep mode, the reset state, or standby mode.
21.8 Usage Notes
21.8.1 Note on Resonator
Since all kinds of characteristics of the resonator are closely related to the board design by the
user, use the example of resonator connection in this document for only reference; be sure to use
an resonator that has been sufficiently evaluated by the user. Consult with the resonator
manufacturer about the resonator circuit ratings which vary depending on the stray capacitances of
the resonator and installation circuit. Make sure the voltage applied to the oscillation pins do not
exceed the maximum rating.
21.8.2 Notes on Board Design
When using a crystal resonator, the crystal resonator and its load capacitors should be placed as
close as possible to the EXTAL and XTAL pins. Other signal lines should be routed away from
the oscillation circuit to prevent inductive interference with the correct oscillation as shown in
figure 21.5.
C
L2
Signal A Signal B
C
L1
This LSI
XTAL
EXTAL
Prohibited
Figure 21.5 Note on Board Design of Oscillation Circuit Section