Datasheet

Section 21 Clock Pulse Generator
Rev. 3.00 Sep. 28, 2009 Page 628 of 710
REJ09B0384-0300
21.2 PLL Multiplier Circuit
The PLL multiplier circuit generates a clock of 4 times the frequency of its input clock. The
frequency ranges of the multiplied clock are shown in table 21.5.
Table 21.3 Ranges of Multiplied Clock Frequency
Input Clock (MHz) Multiplier System Clock (MHz)
Crystal Resonator, 5 to 6.25 4 20 to 25
External Clock
21.3 Medium-Speed Clock Divider
The medium-speed clock divider divides the system clock (φ), and generates φ/2, φ/4, φ/8, φ/16,
and φ/32 clocks.
21.4 Bus Master Clock Select Circuit
The bus master clock select circuit selects a clock to supply the bus master with either the system
clock (φ) or medium-speed clock (φ/2, φ/4, φ/8, φ/16, or φ/32) by the SCK2 to SCK0 bits in
SBYCR.
21.5 Subclock Input Circuit
The subclock input circuit controls subclock input from the EXCL pin. To use the subclock, a
32.768-kHz external clock should be input from the EXCL pin. At this time, the P56DDR bit in
P5DDR should be cleared to 0, and the EXCLE bit in LPWRCR should be set to 1.
When the subclock is not used, subclock input should not be enabled.
21.6 Subclock Waveform Shaping Circuit
To remove noise from the subclock input at the EXCL pin, the subclock is sampled by a divided φ
clock. The sampling frequency is set by the NESEL bit in LPWRCR.