Datasheet

Section 20 Boundary Scan (JTAG)
Rev. 3.00 Sep. 28, 2009 Page 621 of 710
REJ09B0384-0300
20.6 Usage Notes
1. A reset must always be executed by driving the ETRST pin to 0, regardless of whether or not
the JTAG is to be activated. The ETRST pin must be held low for 20 ETCK clock cycles. For
details, see section 24, Electrical Characteristics. To activate the JTAG after a reset, drive the
ETRST pin to 1 and specify the ETCK, ETMS, and ETDI pins to any value. If the JTAG is not
to be activated, drive the ETRST, ETCK, ETMS, and ETDI pins to 1 or the high-impedance
state.
2. The following must be considered when the power-on reset signal is applied to the ETRST pin.
⎯ The reset signal must be applied at power-on.
⎯ To prevent the LSI system operation from being affected by the ETRST pin of the board
tester, circuits must be separated.
⎯ Alternatively, to prevent the ETRST pin of the board tester from being affected by the LSI
system reset, circuits must be separated.
Figure 20.3 shows a design example of the reset signal circuit wherein no reset signal
interference occurs.
Power-on
reset circuit
Board edge pin
System reset
ETRST
RES
ETRST
This LSI
Figure 20.3 Reset Signal Circuit Without Reset Signal Interference
3. The registers are not initialized in standby mode. If the ETRST pin is set to 0 in standby mode,
IDCODE mode will be entered.
4. The frequency of the ETCK pin must be lower than that of the system clock. For details, see
section 24, Electrical Characteristics.
5. Data input/output in serial data transfer starts from the LSB. Figures 20.4 and 20.5 shows
examples of serial data input/output.
6. When data that exceeds the number of bits of the register connected between the ETDI and
ETDO pins is serially transferred, the serial data that exceeds the number of register bits and
output from the ETDO pin is the same as that input from the ETDI pin.
7. If the JTAG serial transfer sequence is disrupted, the ETRST pin must be reset. Transfer
should then be retried, regardless of the transfer operation.