Datasheet

Section 20 Boundary Scan (JTAG)
Rev. 3.00 Sep. 28, 2009 Page 619 of 710
REJ09B0384-0300
In a PRELOAD operation, an initial value is set in the parallel output latch of the boundary scan
register from the scan path prior to the EXTEST instruction. Without a PRELOAD operation,
when the EXTEST instruction was executed an undefined value would be output from the output
pin until completion of the initial scan sequence (transfer to the output latch) (with the EXTEST
instruction, the parallel output latch value is constantly output to the output pin).
(3) EXTEST (Instruction code: B'0000)
The EXTEST instruction is provided to test external circuitry when this LSI is mounted on a
printed circuit board. When this instruction is executed, output pins are used to output test data
(previously set by the SAMPLE/PRELOAD instruction) from the boundary scan register to the
printed circuit board, and input pins are used to latch test results into the boundary scan register
from the printed circuit board. If testing is carried out by using the EXTEST instruction N times,
the Nth test data is scanned in when test data (N-1) is scanned out.
Data loaded into the output pin boundary scan register in the Capture-DR state is not used for
external circuit testing (it is replaced by a shift operation).
(4) CLAMP (Instruction code: B'0010)
When the CLAMP instruction is enabled, the output pin outputs the value of the boundary scan
register that has been previously set by the SAMPLE/PRELOAD instruction. While the CLAMP
instruction is enabled, the state of the boundary scan register maintains the previous state
regardless of the state of the TAP controller.
A bypass register is connected between the ETDI and ETDO pins. The related circuit operates in
the same way when the BYPASS instruction is enabled.
(5) HIGHZ (Instruction code: B'0011)
When the HIGHZ instruction is enabled, all output pins enter a high-impedance state. While the
HIGHZ instruction is enabled, the state of the boundary scan register maintains the previous state
regardless of the state of the TAP controller.
A bypass register is connected between the ETDI and ETDO pins. The related circuit operates in
the same way when the BYPASS instruction is enabled.