Datasheet

Section 2 CPU
Rev. 3.00 Sep. 28, 2009 Page 29 of 710
REJ09B0384-0300
2.6 Instruction Set
The H8S/2600 CPU has 69 instructions. The instructions are classified by function in table 2.1.
Table 2.1 Instruction Classification
Function Instructions Size Types
Data transfer MOV B/W/L 5
POP*
1
, PUSH*
1
W/L
LDM, STM L
MOVFPE*
3
, MOVTPE*
3
B
ADD, SUB, CMP, NEG B/W/L 23 Arithmetic
operation
ADDX, SUBX, DAA, DAS B
INC, DEC B/W/L
ADDS, SUBS L
MULXU, DIVXU, MULXS, DIVXS B/W
EXTU, EXTS W/L
TAS*
4
B
MAC, LDMAC, STMAC, CLRMAC ⎯
Logic operations AND, OR, XOR, NOT B/W/L 4
Shift SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR B/W/L 8
Bit manipulation BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND,
BIAND, BOR, BIOR, BXOR, BIXOR
B 14
Branch Bcc*
2
, JMP, BSR, JSR, RTS ⎯ 5
System control TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP ⎯ 9
Block data transfer EEPMOV ⎯ 1
Total: 69
Notes: B-byte; W-word; L-longword.
1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+,Rn and MOV.W Rn,@-SP.
POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+,ERn and
MOV.L ERn,@-SP.
2. Bcc is the general name for conditional branch instructions.
3. Cannot be used in this LSI.
4. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.