Datasheet

Section 20 Boundary Scan (JTAG)
Rev. 3.00 Sep. 28, 2009 Page 609 of 710
REJ09B0384-0300
20.3.1 Instruction Register (SDIR)
SDIR is a 32-bit register. JTAG instructions can be transferred to SDIR by serial input from the
ETDI pin. SDIR can be initialized when the ETRST pin is low or the TAP controller is in the
Test-Logic-Reset state, but is not initialized by a reset or in standby mode.
Only 4-bit instructions can be transferred to SDIR. If an instruction exceeding 4 bits is input, the
last 4 bits of the serial data will be stored in SDIR.
Bit Bit Name
Initial
Value
R/W Description
31
30
29
28
TS3
TS2
TS1
TS0
1
1
1
0
R/W
R/W
R/W
R/W
Test Set Bits
0000: EXTEST mode
0001: Setting prohibited
0010: CLAMP mode
0011: HIGHZ mode
0100: SAMPLE/PRELOAD mode
0101: Setting prohibited
: :
1101: Setting prohibited
1110: IDCODE mode (Initial value)
1111: BYPASS mode
27 to 14 ⎯ All 0 R Reserved
These bits are always read as 0 and cannot be modified.
13 ⎯ 1 R Reserved
This bit is always read as 1 and cannot be modified.
12 ⎯ 0 R Reserved
This bit is always read as 0 and cannot be modified.
11 ⎯ 1 R Reserved
This bit is always read as 1 and cannot be modified.
10 to 1 ⎯ All 0 R Reserved
These bits are always read as 0 and cannot be modified.
0 ⎯ 1 R Reserved
This bit is always read as 1 and cannot be modified.