Datasheet

Section 20 Boundary Scan (JTAG)
Rev. 3.00 Sep. 28, 2009 Page 608 of 710
REJ09B0384-0300
20.3 Register Descriptions
The JTAG has the following registers.
• Instruction register (SDIR)
• Bypass register (SDBPR)
• Boundary scan register (SDBSR)
• ID code register (SDIDR)
Instructions can be input to the instruction register (SDIR) by serial transfer from the test data
input pin (ETDI). Data from SDIR can be output via the test data output pin (ETDO). The bypass
register (SDBPR) is a 1-bit register to which the ETDI and ETDO pins are connected in BYPASS,
CLAMP, or HIGHZ mode. The boundary scan register (SDBSR) is a 210-bit register to which the
ETDI and ETDO pins are connected in SAMPLE/PRELOAD or EXTEST mode. The ID code
register (SDIDR) is a 32-bit register; a fixed code can be output via the ETDO pin in IDCODE
mode. All registers cannot be accessed directly by the CPU.
Table 20.2 shows the kinds of serial transfer possible with each JTAG register.
Table 20.2 JTAG Register Serial Transfer
Register Serial Input Serial Output
SDIR Possible Possible
SDBPR Possible Possible
SDBSR Possible Possible
SDIDR Impossible Possible