Datasheet

Section 20 Boundary Scan (JTAG)
Rev. 3.00 Sep. 28, 2009 Page 607 of 710
REJ09B0384-0300
20.2 Input/Output Pins
Table 20.1 shows the JTAG pin configuration.
Table 20.1 Pin Configuration
Pin Name Abbreviation I/O Function
Test clock ETCK Input Test Clock Input
Provides an independent clock supply to the
JTAG. As the clock input to the ETCK pin is
supplied directly to the JTAG, a clock waveform
with a duty cycle close to 50% should be input. For
details, see section 24, Electrical Characteristics.
Test mode select ETMS Input Test Mode Select Input
Sampled on the rise of the ETCK pin. The ETMS
pin controls the internal state of the TAP controller.
Test data input ETDI Input Serial Data Input
Performs serial input of instructions and data for
JTAG registers. ETDI is sampled on the rise of the
ETCK pin.
Test data output ETDO Output Serial Data Output
Performs serial output of instructions and data
from JTAG registers. Transfer is performed in
synchronization with the ETCK pin. If there is no
output, the ETDO pin goes to the high-impedance
state.
Test reset ETRST Input Test Reset Input Signal
Initializes the JTAG asynchronously.