Datasheet

Section 19 Flash Memory
Rev. 3.00 Sep. 28, 2009 Page 572 of 710
REJ09B0384-0300
4. When a bus master other than the CPU, such as the DTC, gets bus mastership during
programming/erasing.
Error protection is cancelled only by a reset or by hardware-standby mode. Note that the reset
should be released after the reset period of 100 μs which is longer than normal. Since high
voltages are applied during programming/erasing of the flash memory, some voltage may remain
after the error-protection state has been entered. For this reason, it is necessary to reduce the risk
of damage to the flash memory by extending the reset period so that the charge is released.
The state-transition diagram in figure 19.16 shows transitions to and from the error-protection
state.
Reset or hardware
standby
(Hardware protection)
Program mode
Erase mode
Error protection mode
Error-protection mode
(Software standby)
Read disabled
Programming/erasing
enabled
FLER = 0
Read disabled
Programming/erasing disabled
FLER = 0
Read enabled
Programming/erasing disabled
FLER = 1
Read disabled
programming/erasing disabled
FLER = 1
RES = 0 or STBY = 0
Error occurrence
Error occurred
(Software standby)
RES = 0 or
STBY = 0
Software-standby mode
Cancel
software-standby mode
RES = 0 or
STBY = 0
Program/erase interface
register is in its initial state.
Program/erase interface
register is in its initial state.
Figure 19.16 Transitions to Error-Protection State