Datasheet

Section 19 Flash Memory
Rev. 3.00 Sep. 28, 2009 Page 528 of 710
REJ09B0384-0300
Table 19.4 Parameters and Target Modes
Name of
Parameter
Abbrevia-
tion
Down
Load
Initializa-
tion
Program-
ming
Erasure R/W
Initial
Value
Alloca-
tion
Download pass/fail
result
DPFR
⎯ ⎯ ⎯
R/W Undefined
On-chip
RAM*
Flash pass/fail
result
FPFR ⎯ R/W Undefined R0L of
CPU
Flash
programming/
erasing frequency
control
FPEFEQ ⎯ ⎯ ⎯ R/W Undefined ER0 of
CPU
Flash multipurpose
address area
FMPAR ⎯ ⎯ ⎯ R/W Undefined ER1 of
CPU
Flash multipurpose
data destination
area
FMPDR ⎯ ⎯ ⎯ R/W Undefined ER0 of
CPU
Flash erase block
select
FEBS ⎯ ⎯ ⎯ R/W Undefined R0L of
CPU
Note: * A single byte of the start address to download an on-chip program, which is specified by
FTDAR