Datasheet

Section 19 Flash Memory
Rev. 3.00 Sep. 28, 2009 Page 517 of 710
REJ09B0384-0300
19.2 Input/Output Pins
Table 19.2 shows the flash memory pin configuration.
Table 19.2 Pin Configuration
Pin Name Input/Output Function
RES Input Reset
FWE Input Flash memory programming/erasing enable pin
MD2 Input Sets operating mode of this LSI
MD1 Input Sets operating mode of this LSI
TxD1 Output Serial transmit data output (used in boot mode)
RxD1 Input Serial receive data input (used in boot mode)
19.3 Register Descriptions
The registers/parameters which control flash memory are shown in the following. To read from or
write to these registers/parameters, the FLSHE bit in the serial timer control register (STCR) must
be set to 1. For details on STCR, see section 3.2.3, Serial Timer Control Register (STCR).
• Flash code control status register (FCCS)
• Flash program code select register (FPCS)
• Flash erase code select register (FECS)
• Flash key code register (FKEY)
• Flash MAT select register (FMATS)
• Flash transfer destination address register (FTDAR)
• Download pass/fail result (DPFR)
• Flash pass/fail result (FPFR)
• Flash multipurpose address area (FMPAR)
• Flash multipurpose data destination area (FMPDR)
• Flash erase Block select (FEBS)
• Flash programming/erasing frequency control (FPEFEQ)
There are several operating modes for accessing flash memory, for example, read mode/program
mode.