Datasheet
Section 17 A/D Converter
Rev. 3.00 Sep. 28, 2009 Page 497 of 710
REJ09B0384-0300
(1)
(2)
t
D
t
SPL
t
CONV
Pφ
Address
Write signal
Input sampling
timing
ADF
[Legend]
(1): ADCSR write cycle
(2): ADCSR address
t
D
: A/D conversion start delay
t
SPL
: Input sampling time
t
CONV
: A/D conversion time
Figure 17.4 A/D Conversion Timing