Datasheet

Section 17 A/D Converter
Rev. 3.00 Sep. 28, 2009 Page 496 of 710
REJ09B0384-0300
17.4.3 Input Sampling and A/D Conversion Time
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input when the A/D conversion start delay time (t
D
) passes after the ADST bit in ADCSR is set to
1, then starts A/D conversion. Figure 17.4 shows the A/D conversion timing. Table 17.3 indicates
the A/D conversion time.
As indicated in figure 17.4, the A/D conversion time (t
CONV
) includes t
D
and the input sampling time
(t
SPL
). The length of t
D
varies depending on the timing of the write access to ADCSR. The total
conversion time therefore varies within the ranges indicated in table 17.3.
In scan mode, the values given in table 17.3 apply to the first conversion time. In the second and
subsequent conversions, the conversion time is as shown in table 17.4. In either case, set the CKS1
and CKS0 bits in ADCR so that the conversion time falls within the range of A/D conversion
characteristics.