Datasheet

Section 17 A/D Converter
Rev. 3.00 Sep. 28, 2009 Page 495 of 710
REJ09B0384-0300
4. The ADST bit is not automatically cleared to 0 and steps 2 to 3 are repeated as long as the
ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops and the
A/D converter enters the idle state. After that, when the ADST bit is set to 1, the operation
starts from the first channel again.
ADST
ADF
ADDRA
ADDRB
ADDRC
ADDRD
*
2
Set*
1
Clear*
1
Clear*
1
State of channel 0
(AN0)
State of channel 1
(AN1)
State of channel 2
(AN2)
State of channel 3
(AN3)
Idle Idle Idle
Idle
Idle
Continuous execution of A/D conversion
Idle Idle
Idle
Idle
Transfer
A/D conversion 1
A/D conversion 2
A/D conversion 3
A/D conversion 4
A/D conversion time
Result of A/D conversion 1 Result of A/D conversion 4
Result of A/D conversion 2
Result of A/D conversion 3
1. indicates execution of a software instruction.
2. The data being converted is ignored
Notes :
A/D conversion 5
Figure 17.3 Example of A/D Converter Operation
(When Channels AN0 to AN3 are Selected in Scan Mode)