Datasheet

Section 17 A/D Converter
Rev. 3.00 Sep. 28, 2009 Page 490 of 710
REJ09B0384-0300
17.3.2 A/D Control/Status Register (ADCSR)
The ADCSR controls the operation of the A/D conversion.
Bit Bit Name
Initial
Value
R/W Description
7 ADF 0 R/(W)* A/D End Flag
A status flag that indicates the end of A/D conversion.
This flag indicates that the results of A/D conversion are
stored in the A/D data registers.
[Setting conditions]
• When A/D conversion ends in single mode
• When A/D conversion ends on all channels specified
in scan mode
[Clearing conditions]
• When 0 is written after reading ADF = 1
• When DTC starts by an ADI interrupt and ADDR is
read
6 ADIE 0 R/W A/D Interrupt Enable
Enables ADI interrupt by ADF when this bit is set to 1
5 ADST 0 R/W A/D Start
Clearing this bit to 0 stops A/D conversion and enters the
idle state. Setting this bit to 1 starts A/D conversion. In
single mode, this bit is cleared to 0 automatically when
conversion on the specified channel ends. In scan mode,
conversion continues sequentially on the specified
channels until this bit is cleared to 0 by software, a reset,
or a transition to the hardware standby mode.
4 ⎯ 0 R Reserved
This is a read-only bit and cannot be modified.