Datasheet

Section 17 A/D Converter
Rev. 3.00 Sep. 28, 2009 Page 489 of 710
REJ09B0384-0300
17.3.1 A/D Data Registers A to H (ADDRA to ADDRH)
The ADDR are eight 16-bit read-only registers, ADDRA to ADDRH, which store the results of
A/D conversion. The ADDR registers, which store a conversion result for each channel, are shown
in table 17.2.
The converted 10-bit data is stored to bits 15 to 6. The lower 6-bit data is always read as 0.
The data bus between the CPU and the A/D converter is 16-bit width and can be read directly
from the CPU. The ADDR must always be accessed in 16-bit unit. They cannot be accessed in 8-
bit unit.
The results of A/D conversion are stored in each registers, when the ADF flag is set to 1.
Table 17.2 Analog Input Channels and Corresponding ADDR Registers
Analog Input Channel A/D Data Register to Store A/D Conversion Results
AN0 ADDRA
AN1 ADDRB
AN2 ADDRC
AN3 ADDRD
AN4 ADDRE
AN5 ADDRF
AN6 ADDRG
AN7 ADDRH