Datasheet

Section 16 LPC Interface (LPC)
Rev. 3.00 Sep. 28, 2009 Page 474 of 710
REJ09B0384-0300
Table 16.6 Scope of Initialization in Each LPC Interface Mode
Items Initialized
System
Reset
LPC Reset
LPC
Shutdown
LPC transfer cycle sequencer (internal state), LPCBSY and ABRT
flags
Initialized Initialized Initialized
SERIRQ transfer cycle sequencer (internal state), CLKREQ and
IRQBSY flags
Initialized Initialized Initialized
LPC interface flags
(IBF1, IBF2, IBF3A, IBF3B, MWMF, C/D1, C/D2, C/D3, OBF1,
OBF2, OBF3A, OBF3B, SWMF, DBU, SMICFLG, SMICIR0, BTSR0,
BTSR1, BTIMSR, BTFVSR0, BTFVSR1)
Initialized Initialized Retained
Host interrupt enable bits
(IRQ1E1, IRQ12E1, SMIE2, IRQ6E2, IRQ9E2 to IRQ11E2, SMIE3B,
SMIE3A, IRQ6E3, IRQ9E3 to IRQ11E3, SELREQ, IEDIR2 to
IEDIR3), Q/C flag
Initialized Initialized Retained
LRST flag Initialized (0) Can be
set/cleared
Can be
set/cleared
SDWN flag Initialized (0) Initialized (0) Can be
set/cleared
LRSTB bit Initialized (0) HR: 0
SR: 1
0 (can be
set)
SDWNB bit Initialized (0) Initialized (0) HS: 0
SS: 1
SDWNE bit Initialized (0) Initialized (0) HS: 1
SS: 0 or 1
LPC interface operation control bits
(LPC3E to LPC1E, LADR1 to LADR3, IBFIE1 to IBFIE3, SELSTR3,
SELIRQ1, SELSMI, SELIRQ3 to SELIRQ15, HICR4, HICR5, HISEL,
BTCSR0, BTCSR1)
Initialized Retained Retained
LRESET signal Input (port
function
Input Input
LAD3 to LAD0, LFRAME, LCLK, SERIRQ, CLKRUN signals Input Hi-Z
Note: System reset: Reset by STBY input, RES input, or WDT overflow
LPC reset: Reset by LPC hardware reset (HR) or LPC software reset (SR)
LPC shutdown: Reset by LPC software shutdown (SS)