Datasheet

Section 16 LPC Interface (LPC)
Rev. 3.00 Sep. 28, 2009 Page 473 of 710
REJ09B0384-0300
16.4.5 LPC Interface Shutdown Function
The LPC software shutdown state is controlled by the SDWNB bit. The LPC interface enters the
reset state by itself, and is no longer affected by external signals other than the LRESET and
LPCPD signals.
Placing the slave in sleep mode or software standby mode is effective in reducing current
dissipation in the shutdown state.
In the LPC shutdown state, the LPC's internal state and some register bits are initialized. The order
of priority of LPC shutdown and reset states is as follows.
1. System reset (reset by RES pin input, or WDT0 overflow)
All register bits, including bits LPC3E to LPC1E, are initialized.
2. LPC hardware reset (reset by LRESET pin input)
LRSTB, SDWNE, and SDWNB bits are cleared to 0.
3. LPC software reset (reset by LRSTB)
SDWNE and SDWNB bits are cleared to 0.
4. LPC software shutdown
The scope of the initialization in each mode is shown in table 16.9.