Datasheet

Section 16 LPC Interface (LPC)
Rev. 3.00 Sep. 28, 2009 Page 469 of 710
REJ09B0384-0300
Wait for BUSY = 0
Wait for
TX_DATA_RDY = 1
Host confirms the BUSY bit in SMICFLG.
The bit indicates slave (this LSI) is ready for receiving a new control code.
When BUSY = 1, access from host is disabled.
Slave confirms the rising edge of the BUSY bit in SMICFLG.
The BUSYI bit in SMICIR0 is set.
Host confirms the falling edge of the BUSY bit in SMICFLG.
An interrupt is generated.
Slave clears the TX_DATA_RDY bit in SMICFLG.
Host confirms the TX_DATA_RDY bit in SMICFLG.
The confirmation is unnecessary when Write Start control is issued.
Host writes the Write control code in SMICCSR.
Host writes transfer data in SMICDTR.
Slave reads transfer data in SMICDTR according to
Write control code.
Slave writes the status code to SMICCSR to notify
the processing completion status.
Slave clears the BUSY bit in SMICFLG to indicate
transfer completion.
Slave confirms that status code is read from SMICCSR
by host.
The STARI bit in SMICIR0 is set.
Slave confirms that valid data is written to SMICDTR
by host.
The HDTWI bit in SMICIR0 is set.
Slave reads the control code in SMICCSR.
Host confirms the status code in SMICCSR.
In the case of normal completion, the status code is reflected to the next step.
In the case of abnormal completion, the status code is READY and an error
is kept.
Host sets the BUSY bit in SMICFLG.
Write control code
Write transfer data
BUSY = 1
TX_DATA_RDY = 0
Write status code
BUSY = 0
Generate slave
interrupt
Generate host
interrupt
Generate slave
interrupt
Generate slave
interrupt
Generate slave
interrupt
Normal
Abnormal
Read control code
Read transfer data
Read status code
A
A
Bit that indicates slave is ready for write transfer.
Issues when slave is ready for the next write transfer.
HostSlave
Slave waits for the BUSY bit in SMICFLG is set.
Slave confirms that control code is written to SMICCSR
by host.
The CTLWI bit in SMICIR0 is set.
Figure 16.4 SMIC Write Transfer Flow