Datasheet

Section 16 LPC Interface (LPC)
Rev. 3.00 Sep. 28, 2009 Page 466 of 710
REJ09B0384-0300
16.4 Operation
16.4.1 LPC interface Activation
The LPC interface is activated by setting any one of bits LPC3E to LPC1E in HICR0 to 1. When
the LPC interface is activated, the related I/O port pins (PE7 to PE0) function as dedicated LPC
interface input/output pins.
Use the following procedure to activate the LPC interface after a reset release.
1. Read the signal line status and confirm that the LPC module can be connected. Also check that
the LPC module is initialized internally.
2. When using channels 1 and 2, set LADR1 and LADR2 to determine the I/O address.
3. When using channel 3, set LADR3 to determine the I/O address and whether bidirectional data
registers are to be used.
4. Set the enable bit (LPC3E to LPC1E) for the channel to be used. Also set SCIFE if the SCIF is
to be used.
5. Set the selection bits for other functions (SDWNE, IEDIR).
6. As a precaution, clear the interrupt flags (LRST, SDWN, ABRT, and OBF). Read IDR or
TWR15 to clear IBF.
7. Set receive complete interrupt enable bits (IBFIE3 to IBFIE1, and ERRIE) as necessary.
16.4.2 LPC I/O Cycles
There are 12 types of LPC transfer cycle: LPC memory read, LPC memory write, I/O read, I/O
write, DMA read, DMA write, bus master memory read, bus master memory write, bus master I/O
read, bus master I/O write, FW memory read, and FW memory write. Of these, the LPC of this
LSI supports I/O read and I/O write.