Datasheet

Section 16 LPC Interface (LPC)
Rev. 3.00 Sep. 28, 2009 Page 464 of 710
REJ09B0384-0300
R/W
Bit Bit Name Initial Value Slave Host Description
4
3
2
OEM3
OEM2
OEM1
0
0
0
R/W
R/W
R/W
R/(W)*
4
R/(W)*
4
R/(W)*
4
User Defined Bit
These bits are defined by the user and are valid
only when set to 1 by a 0 written from the host.
0: [Clearing condition]
When the slave writes a 0, after a 1 has been
read from OEM.
1: [Setting condition]
When the slave writes a 1, after a 0 has been
read from OEM, or when the host writes a 0.
1 B2H_IRQ 0 R/(W)*
1
R/(W)*
3
BMC to HOST Interrupt
Informs the host that an interrupt has been
requested when the BEVT_ATN or B2H_ATN
bit has been set. The SERIRQ is not issued. To
generate the SERIRQ, it should be issued by
the program.
0: B2H_IRQ interrupt is not requested
[Clearing condition]
When the host writes a 1.
1: B2H_IRQ interrupt is requested
[Setting condition]
When the slave writes a 1, after a 0 has been
read from B2H_IRQ
0 B2H_IRQ_EN 0 R R/W BMC to HOST Interrupt Enable
Enables or disables the B2H_IRQ interrupt
which is an interrupt source from the slave to
the host.
0: B2H_IRQ interrupt is disabled
[Clearing condition]
When a 0 is written by the host.
1: B2H_IRQ interrupt is enabled
[Setting condition]
When a 1 is written by the host.
Notes: 1. Only 1 can be written to set this flag.
2. Only 0 can be written to clear this flag.
3. Only 1 can be written to clear this flag.
4. Only 0 can be written to set this flag.