Datasheet

Section 16 LPC Interface (LPC)
Rev. 3.00 Sep. 28, 2009 Page 449 of 710
REJ09B0384-0300
R/W
Bit Bit Name Initial Value Slave Host Description
2 STARI 0 R/(W)* ⎯ Status Code Receive End Interrupt
This is a status flag that indicates that the host has
finished receiving the status code from SMICCSR.
When the IBFIE3 bit and STARIE bit are set to 1, the
IBFI3 interrupt is requested to the slave.
0: Status code receive wait state
[Clearing condition]
After the slave reads STARI = 1, writes 0 to this bit.
1: Status code receive end
[Setting condition]
When the host reads the status code of SMICCSR.
1 CTLWI 0 R/(W)* ⎯ Control Code Transmission End Interrupt
This is a status flag that indicates that the host has
finished transmitting the control code to SMICCSR.
When the IBFIE3 bit and CTLWIE bit are set to1, the
IBFI3 interrupt is requested to the slave.
0: Control code transmission wait state
[Clearing condition]
After the slave reads CTLWI = 1, writes 0 to this bit.
1: Control code transmission end
[Setting condition]
When the host writes the status code to SMICCSR.
0 BUSYI R/(W)* ⎯ Transfer Start Interrupt
This is a status flag that indicates that the host starts
transferring. When the IBFIE3 bit and BUSYIE bit
are set to 1, the IBFI3 interrupt is requested to the
slave.
0: Transfer start wait state
[Clearing condition]
After the slave reads BUSYI = 1, writes 0 to this bit.
1: Transfer start
[Setting condition]
When the rising edge of the BUSY bit in SMICFLG is
detected.
Note: * Only 0 can be written to clear the flag.