Datasheet

Section 16 LPC Interface (LPC)
Rev. 3.00 Sep. 28, 2009 Page 443 of 710
REJ09B0384-0300
16.3.13 SERIRQ Control Register 4 (SIRQCR4)
SIRQCR4 controls LPC interrupt requests to the host.
R/W
Bit Bit Name
Initial
Value
Slave Host Description
7 IRQ15E 0 R/W ⎯ Host IRQ15 Interrupt Enable
0: Disables HIRQ15 interrupt request by IRQ15E
1: Enables HIRQ15 interrupt request
6 IRQ14E 0 R/W ⎯ Host IRQ14 Interrupt Enable
0: Disables HIRQ14 interrupt request by IRQ14E
1: Enables HIRQ14 interrupt request
5 IRQ13E 0 R/W ⎯ Host IRQ13 Interrupt Enable
0: Disables HIRQ13 interrupt request by IRQ13E
1: Enables HIRQ13 interrupt request
4 IRQ8 0 R/W ⎯ Host IRQ8 Interrupt Enable
0: Disables HIRQ8 interrupt request by IRQ8E
1: Enables HIRQ8 interrupt request
3 IRQ7 0 R/W ⎯ Host IRQ7 Interrupt Enable
0: Disables HIRQ7 interrupt request by IRQ7E
1: Enables HIRQ7 interrupt request
2 IRQ5 0 R/W ⎯ Host IRQ5 Interrupt Enable
0: Disables HIRQ5 interrupt request by IRQ5E
1: Enables HIRQ5 interrupt request
1 IRQ4 1 R/W ⎯ Host IRQ4 Interrupt Enable
0: Disables HIRQ4 interrupt request by IRQ4E
1: Enables HIRQ4 interrupt request
0 IRQ3 1 R/W ⎯ Host IRQ3 Interrupt Enable
0: Disables HIRQ3 interrupt request by IRQ3E
1: Enables HIRQ3 interrupt request