Datasheet

Section 16 LPC Interface (LPC)
Rev. 3.00 Sep. 28, 2009 Page 442 of 710
REJ09B0384-0300
16.3.12 SERIRQ Control Register 2 (SIRQCR2)
SIRQCR2 contains bits that enable or disable SERIRQ interrupt requests and select the host
interrupt request outputs.
R/W
Bit Bit Name Initial Value Slave Host Description
7 IEDIR3 0 R/W ⎯ Interrupt Enable Direct Mode 3
Selects whether an SERIRQ interrupt generation of
LPC channel 3 is affected only by a host interrupt
enable bit or by an OBF flag in addition to the
enable bit.
0: A host interrupt is generated when both the
enable bit and the corresponding OBF flag are
set.
1: A host interrupt is generated when the enable bit
is set.
6 to 0 ⎯ All 0 R/W ⎯ Reserved
The initial value should not be changed.