Datasheet
Section 16 LPC Interface (LPC)
Rev. 3.00 Sep. 28, 2009 Page 441 of 710
REJ09B0384-0300
R/W
Bit Bit Name Initial Value Slave Host Description
1 IRQ9E2 0 R/W ⎯ Host IRQ9 Interrupt Enable 2
Enables or disables an HIRQ9 interrupt request
when OBF2 is set by an oDR2 write.
0: HIRQ9 interrupt request by OBF2 and IRQE9E2
is disabled.
[Clearing conditions]
• Writing 0 to IRQ9E2
• LPC hardware reset, LPC software reset
• Clearing OBF2 to 0 (when IEDIR2 = 0)
1: [When IEDIR2 = 0]
HIRQ9 interrupt request by setting OBF2 to 1 is
enabled.
[When IEDIR2 = 1]
HIRQ9 interrupt is requested
[Setting condition]
Writing 1 after reading IRQ9E2 = 0
0 IRQ6E2 0 R/W ⎯ Host IRQ6 Interrupt Enable 2
Enables or disables an HIRQ6 interrupt request
when OBF2 is set by an oDR2 write.
0: HIRQ6 interrupt request by OBF2 and IRQE6E2
is disabled.
[Clearing conditions]
• Writing 0 to IRQ6E2
• LPC hardware reset, LPC software reset
• Clearing OBF2 to 0 (when IEDIR2 = 0)
1: [When IEDIR2 = 0]
HIRQ6 interrupt request by setting OBF2 to 1 is
enabled.
[When IEDIR2 = 1]
HIRQ6 interrupt is requested.
[Setting condition]
Writing 1 after reading IRQ6E2 = 0