Datasheet

Section 16 LPC Interface (LPC)
Rev. 3.00 Sep. 28, 2009 Page 439 of 710
REJ09B0384-0300
R/W
Bit Bit Name Initial Value Slave Host Description
5 IRQ9E3 0 R/W ⎯ Host IRQ9 Interrupt Enable 3
Enables or disables an HIRQ9 interrupt request
when OBF3A is set by an ODR3 write.
0: HIRQ9 interrupt request by OBF3A and IRQE9E3
is disabled.
[Clearing conditions]
• Writing 0 to IRQ9E3
• LPC hardware reset, LPC software reset
• Clearing OBF3A to 0 (when IEDIR3 = 0)
1: [When IEDIR3 = 0]
HIRQ9 interrupt request by setting OBF3A to 1 is
enabled.
[When IEDIR3 = 1]
HIRQ9 interrupt is requested.
[Setting condition]
Writing 1 after reading IRQ9E3 = 0
4 IRQ6E3 0 R/W ⎯ Host IRQ6 Interrupt Enable 3
Enables or disables an HIRQ6 interrupt request
when OBF3A is set by an ODR3 write.
0: HIRQ6 interrupt request by OBF3A and IRQE6E3
is disabled.
[Clearing conditions]
• Writing 0 to IRQ6E3
• LPC hardware reset, LPC software reset
• Clearing OBF3A to 0 (when IEDIR3 = 0)
1: [When IEDIR3 = 0]
HIRQ6 interrupt request by setting OBF3A to 1 is
enabled.
[When IEDIR3 = 1]
HIRQ6 interrupt is requested
[Setting condition]
Writing 1 after reading IRQ6E3 = 0