Datasheet

Section 16 LPC Interface (LPC)
Rev. 3.00 Sep. 28, 2009 Page 436 of 710
REJ09B0384-0300
R/W
Bit Bit Name Initial Value Slave Host Description
2 SMIE2 0 R/W ⎯ Host SMI Interrupt Enable 2
Enables or disables an SMI interrupt request when
OBF2 is set by an ODR2 write.
0: Host SMI interrupt request by OBF2 and SMIE2 is
disabled
[Clearing conditions]
• Writing 0 to SMIE2
• LPC hardware reset, LPC software reset
• Clearing OBF2 to 0 (when IEDIR2 = 0)
1: [When IEDIR2 = 0]
Host SMI interrupt request by setting OBF2 to 1
is enabled.
[When IEDIR2 = 1]
Host SMI interrupt is requested.
[Setting condition]
Writing 1 after reading SMIE2 = 0
1 IRQ12E1 0 R/W ⎯ Host IRQ12 Interrupt Enable 1
Enables or disables an HIRQ12 interrupt request
when OBF1 is set by an ODR1 write.
0: HIRQ12 interrupt request by OBF1 and IRQ12E1
is disabled.
[Clearing conditions]
• Writing 0 to IRQ12E1
• LPC hardware reset, LPC software reset
• Clearing OBF1 to 0
1: HIRQ12 interrupt request by setting OBF1 to 1 is
enabled.
[Setting condition]
Writing 1 after reading IRQ12E1 = 0