Datasheet

Section 16 LPC Interface (LPC)
Rev. 3.00 Sep. 28, 2009 Page 434 of 710
REJ09B0384-0300
16.3.10 SERIRQ Control Register 0 (SIRQCR0)
SIRQCR0 contains status bits that indicate the SERIRQ operating mode and bits that specify
SERIRQ interrupt sources.
R/W
Bit Bit Name Initial Value Slave Host Description
7 Q/C 0 R ⎯ Quiet/Continuous Mode Flag
Indicates the mode specified by the host at the end
of an SERIRQ transfer cycle (stop frame).
0: Continuous mode
[Clearing conditions]
• LPC hardware reset, LPC software reset
• Specification by SERIRQ transfer cycle stop
frame
1: Quiet mode
[Setting condition]
Specification by SERIRQ transfer cycle stop frame.
6 SELREQ 0 R/W ⎯ Start Frame Initiation Request Select
Selects the condition of a start frame initiation
request when a host interrupt request is cleared in
quiet mode.
0: Start frame initiation is requested when all
interrupt requests are cleared.
1: Start frame initiation is requested when one or
more interrupt requests are cleared.
5 IEDIR2 0 R/W ⎯ Interrupt Enable Direct Mode
Specifies whether LPC channel 2 and channel 3
SERIRQ interrupt source (SMI, IRQ6, IRQ9 to
IRQ11) generation is conditional upon OBF, or is
controlled only by the host interrupt enable bit.
0: Host interrupt is requested when host interrupt
enable and corresponding OBF bits are both set
to 1.
1: Host interrupt is requested when host interrupt
enable bit is set to 1.