Datasheet

Section 16 LPC Interface (LPC)
Rev. 3.00 Sep. 28, 2009 Page 428 of 710
REJ09B0384-0300
• STR2
R/W
Bit Bit Name Initial Value Slave Host Description
7
6
5
4
DBU27
DBU26
DBU25
DBU24
0
0
0
0
R/W
R/W
R/W
R/W
R
R
R
R
Defined by User
The user can use these bits as necessary.
3 C/D2 0 R R Command/Data
When the host writes to IDR2, bit 2 of the I/O
address (when CH2OFFSEL1 = 0) or bit 0 of the I/O
address (when CH2OFFSEL1 = 1) is written to this
bit to indicate whether IDR2 contains data or a
command.
0: Content of input data register (IDR2) is a data
1: Content of input data register (IDR2) is a
command
2 DBU22 0 R/W R Defined by User
The user can use this bit as necessary.
1 IBF2 0 R R Input Data Register Full
Indicates whether or not there is receive data in
IDR2.This bit is an internal interrupt source to the
slave (this LSI).
0: There is not receive data in IDR2.
[Clearing condition]
When the slave reads IDR2
1: There is receive data in IDR2.
[Setting condition]
When the host writes to IDR2 in an I/O write cycle