Datasheet

Section 16 LPC Interface (LPC)
Rev. 3.00 Sep. 28, 2009 Page 427 of 710
REJ09B0384-0300
R/W
Bit Bit Name Initial Value Slave Host Description
1 IBF1 0 R R Input Data Register Full
Indicates whether or not there is receive data in
IDR1. This bit is an internal interrupt source to the
slave processor (this LSI).
0: There is not receive data in IDR1
[Clearing condition]
When the slave processor reads IDR
1: There is receive data in IDR1
[Setting condition]
When the host processor writes to IDR using I/O
write cycle
0 OBF1 0 R/(W)* R Output Data Register Full
Indicates whether or not there is transmit data in
ODR1.
0: There is not transmit data in ODR1
[Clearing condition]
When the host processor reads ODR1 using I/O
read cycle, or the slave processor writes 0 to the
OBF1 bit
1: There is transmit data in ODR1
[Setting condition]
When the slave processor writes to ODR1
Note: * Only 0 can be written to clear the flag.